1. Field of the Invention
The present invention relates to semiconductor devices and a manufacturing method thereof, and more particularly, to a semiconductor device having a bipolar transistor and a manufacturing method thereof.
2. Description of the Background Art
Conventionally, a bipolar transistor is known as one of semiconductor elements. FIG. 22 is a cross section of a semiconductor device including a conventional bipolar transistor. Referring to FIG. 22, a conventional semiconductor device having a bipolar transistor includes a p.sup.+ -type silicon substrate 101; an n.sup.+ -type buried diffusion layer 102 which is formed in a predetermined region on a main surface of p.sup.+ -type silicon substrate 101; an n.sup.- -type epitaxial layer 103 which is formed on the entire main surface of p.sup.+ -type silicon substrate 101; a p.sup.+ -type isolation layer 104 which is formed in a predetermined region of n.sup.- -type epitaxial layer 103; an n.sup.+ -type collector layer 106 which is formed in a predetermined region on a main surface of n.sup.- -type epitaxial layer 103 surrounded by p.sup.+ -type isolation layer 104; a p.sup.+ -type base layer 105 which is formed in a region on the main surface of n.sup.- -type epitaxial layer 103 spaced apart by a predetermined distance from n.sup.+ -type collector layer 106; and an n.sup.+ -type emitter layer 107 which is formed in a predetermined region on a main surface of p.sup.+ -type base layer 105.
Also, a conventional semiconductor device having a bipolar transistor includes an insulating oxide film 109 which is formed on the main surface of n.sup.- -type epitaxial layer 103 and having contact holes 109a, 109b, and 109c formed respectively on n.sup.+ -type emitter layer 107, p.sup.+ -type base layer 105, and n.sup.+ -type collector layer 106; titanium silicide (TiSi.sub.2) films 110a, 110b, and 110c which are formed to contact the surface of n.sup.+ -type emitter layer 107, p.sup.+ -type base layer 105, and n.sup.+ -type collector layer 106 respectively in contact holes 109a, 109b, and 109c; titanium nitride (TiN) films 111a, 111b, and 111c which are formed respectively on titanium silicide films 110a, 110b, and 110c; aluminum interconnection films 112a, 112b, and 112c which are formed respectively on titanium nitride films 111a, 111b, and 111c; and a protection film 113 which is formed to cover the entire surface.
Titanium silicide films 110a, 110b, and 110c are formed to make ohmic contact with n.sup.+ -type emitter layer 107, p.sup.+ -type base layer 105 and n.sup.+ -type collector layer 106 respectively. Titanium nitride films 111a, 111b, and 111c serve as barrier layers for preventing aluminum alloy spike caused by aluminum interconnection layers 112a, 112b, and 112c formed thereon. A collector region is structured by n.sup.- -type epitaxial layer 103 and n.sup.+ collector layer 106 in a region surrounded by p.sup.+ -type isolation layer 104.
FIGS. 23-31 are cross sectional views showing a manufacturing process of a semiconductor device including a conventional bipolar transistor shown in FIG. 22. Referring to FIGS. 23-31, a manufacturing process of a conventional semiconductor device will be described.
As shown in FIG. 23, n.sup.+ -type buried diffusion layer 102 is formed in p.sup.+ -type silicon substrate 101. Then, n.sup.- -type epitaxial layer 103 is formed on the entire surface of p.sup.+ -type silicon substrate 101. p.sup.+ -type isolation layer 104 is formed in a predetermined region of n.sup.- -type epitaxial layer 103. Insulating oxide film 109 is formed on a main surface of n.sup.- -type epitaxial layer 103.
As shown in FIG. 24, p-type impurity is introduced via insulating oxide film 109 into a predetermined region on the main surface of n.sup.- -type epitaxial layer 103 surrounded by p.sup.+ -type isolation layer 104 through, for example, the ion implantation method. Then, p.sup.+ -type base layer 105 having resistance value of 100-1000 .OMEGA./.quadrature., diffusion depth of 0.3-1.5 .mu.m, and surface impurity concentration of about -5.times.10.sup.18 cm.sup.-3 is formed by activating the introduced p-type impurity.
As shown in FIG. 25, a photoresist 120 is formed by using photolithography in a predetermined region on insulating oxide film 109. Using photoresist 120 as a mask, insulating oxide film 109, where an emitter electrode, a base electrode and a collector electrode of the bipolar transistor are to be made, is etched anisotropically, and thereby contact holes 109a, 109b, and 109c are formed. Photoresist 120 is then removed.
As shown in FIG. 26, a photoresist 121 is formed by using photolithography so as to cover the region, where the base electrode of the bipolar transistor is to be made, is formed. Then, n-type impurity such as arsenic ions (As.sup.+) is implanted on the entire surface. Photoresist 121 is then removed. Then, n.sup.+ -type collector layer 106 and n.sup.+ -type emitter layer 107 are formed as shown in FIG. 27 by activating the ion-implanted impurity.
As shown in FIG. 28, titanium (Ti) film 122 having a thickness of the range from about 40 to about 100 nm is formed. Then heat treatment is conducted for about 30 seconds in N.sub.2 atmosphere under the temperature condition of 750.about.850.degree. C. Thereby, titanium silicide films 110a, 110b, and 110c and titanium nitride layer 111 are formed as shown in FIG. 29. More particularly, titanium silicide films 110a, 110b, and 110c are formed by silicide reaction between titanium film 122 (see FIG. 28) and silicon in n.sup.- -type epitaxial layer 103, while the rest of titanium film 122 (see FIG. 28) is nitrided by N.sub.2 gas to be titanium nitride layer 111.
As shown in FIG. 30, aluminum interconnection layer 112 is formed on titanium nitride layer 111. A photoresist 123 is formed by photolithography at a predetermined region on aluminum interconnection layer 112. Using photoresist 123 as a mask, titanium nitride films 111a, 111b, and 111c and aluminum interconnection films 112a, 112b, and 112c are formed as shown in FIG. 31 by etching aluminum interconnection layer 112 and titanium nitride layer 111 anisotropically. Resist 123 is then removed.
Finally, as shown in FIG. 32, protection film 113 is formed on the entire surface. The conventional semiconductor device having a bipolar transistor is thus completed.
As mentioned above, in the conventional semiconductor device having a bipolar transistor, titanium silicide films 110a, 110b, and 110c are formed by utilizing silicide reaction between titanium layer 122 and substrate silicon so as to obtain ohmic contact with n.sup.+ -type emitter layer 107, p.sup.+ -type base layer 105, and n.sup.+ -type collector layer 106.
However, p-type impurity in p.sup.+ -type base layer 105 is taken in titanium silicide film 110b due to silicide reaction between titanium and silicon. FIG. 33 is an impurity profile along line X.sub.1 --X.sub.1 in a step before silicide reaction shown in FIG. 28. FIG. 34 is an impurity profile along line X.sub.2 --X.sub.2 in a step after silicide reaction shown in FIG. 29. Referring to FIGS. 33 and 34, the surface impurity concentration in p.sup.+ -type base layer 105 is about 5.times.10.sup.8 cm.sup.-3 before silicide reaction: however, it is noted that the surface impurity concentration in p.sup.+ -type base layer 105 is lowered to about 5.times.10.sup.16 cm.sup.-3 after silicide reaction. This is because p-type impurity in p.sup.+ -type base layer 105 is taken in titanium silicide (TiSi.sub.2) film 110b which is formed by silicide reaction, as shown in FIG. 34.
FIG. 35 is an impurity profile along line A.sub.1 --A.sub.1 in the semiconductor device which is completed finally as shown in FIG. 32, and FIG. 36 is an impurity profile along line B.sub.1 --B.sub.1 of the same. Referring to FIG. 35, in the impurity profile along line A.sub.1 --A.sub.1 of the finished semiconductor device (see FIG. 32), the impurity concentration in p.sup.+ -type base layer 105 is lowered down to 5.times.10.sup.16 cm.sup.-3 by silicide reaction as described above. Here, as shown in FIG. 36, the impurity concentration in n.sup.+ -type emitter layer 107 (see FIG. 32) is not lowered so much by silicide reaction as p.sup.+ -type base layer 105. This is because n-type impurity is hardly taken in silicide layer generally, and at the same time the impurity concentration in n.sup.+ -type emitter layer 107 was originally high. Accordingly, the impurity concentration in n.sup.+ -type collector layer 106, which is the same n-type as the emitter layer 107, is not so much lowered by silicide reaction. Thus, only p.sup.+ -type base layer 105 is affected by silicide reaction, and, the problem is the decrease of the impurity concentration in p.sup.+ -type base layer 105.
More particularly, the resistance of the base contact increases if the surface impurity concentration of p.sup.+ -type base layer 105 decreases due to silicide reaction. FIG. 37 is a graph showing correlation of the impurity concentration at interface between titanium silicide (TiSi.sub.2) and silicon (Si) and the resistance value of the base contact. Referring to FIG. 37, it is noted that if the impurity concentration at interface between titanium silicide and silicon, i.e., the surface impurity concentration in p.sup.+ -type base layer 105, decreases, then the resistance value of the base contact increases abruptly. More specifically, after silicide reaction the resistance value of the base contact increases up to about 1000 times that before silicide reaction. Hence, the problem was that the operating speed of the bipolar transistor decreased if the resistance value of the base contact increased.
Also, the base contact resistance comes to depend on temperature as the surface impurity concentration in p.sup.+ -type base layer 105 decreases due to silicide reaction. FIG. 38 is a graph showing a relationship of the temperature when the surface impurity concentration N in p.sup.+ -type base layer 105 is not more than 1.0.times.10.sup.17 cm.sup.-3 and of the resistance value of the base contact. Referring to FIG. 38, a remarkable temperature dependency is developed in the resistance of the base contact when the surface impurity concentration N of p.sup.+ -type base layer 105 is lowered to 1.0.times.10.sup.17 cm.sup.-3 or lower. In other words, the resistance of the base contact decreases as the temperature rises. This phenomenon becomes outstanding as the current decreases. This phenomenon is disclosed, for example, in VLSI TECHNOLOGY edited by S. M. Sze, pp. 347-350. Thus, as the temperature dependency is developed in the resistance of the base contact, the circuit characteristics change because of temperature.
Conventionally, the resistance of the base contact increases because the surface impurity concentration in p.sup.+ -type base layer decreases by silicide reaction, causing much temperature dependency of the resistance of the base contact. In addition to silicide reaction, conventionally, oxidization of the surface of p.sup.+ -type base layer or the like causes decrease of the surface impurity concentration of p.sup.+ -type base layer.
The following is a possible structure in order to solve such problems. FIG. 39 is a cross sectional view showing the proposed example. Referring to FIG. 39, a p.sup.++ -type base layer 205 which has a higher impurity concentration compared to the conventional one is applied in this proposal. If p.sup.++ -type base layer 205 of a higher impurity concentration is formed, even though the surface impurity concentration in p.sup.++ -type base layer 205 is decreased by silicide reaction, etc., the decrease of surface impurity concentration to 10.sup.8 cm.sup.-3 or lower can be easily prevented. Accordingly, problems such as increase of the resistance of the base contact and occurrence of temperature dependency of the resistance of the base contact can be solved.
However, when p.sup.++ -type base layer 205 which has a higher impurity concentration is formed, the difference of impurity concentrations at interface between p.sup.++ -type base layer 205 and emitter layer 107 is increased. Thus, it becomes difficult for electrons from n.sup.+ -type emitter layer 107 to pass through p.sup.++ -type base layer 205, and accordingly an amplification factor between an emitter and base is decreased. Also, if the difference of impurity concentrations at interface between p.sup.++ -type base layer 205 and n.sup.+ -type emitter layer 107 becomes large, it leads to electric field concentration, so that the emitter-base reverse breakdown voltage of is decreased. Thus, when p.sup.++ -type base layer 205 having a higher impurity concentration is used for preventing decrease of the surface impurity concentration in the base layer due to silicide reaction, etc., various problems will occur.